RV32I
RV32I registers
The user-visible architectural state is:
- Value of
x0/zerois always 0; writes do not change it. - 31 read/write data registers
x1..x31; pc: the program counter register pointing to the start of the current instruction
Instructions must be stored naturally aligned in little-endian byte order.
Instruction classes
RV32I specification describes 47 instructions:
- computational instructions (21 instructions)
- memory access instructions (10 instructions)
- control flow instructions (8 instructions)
- system instructions (8 instructions, control and status registers)
Major opcodes for classes
op[1:0]=11 for all instructions in RV32I.
| op[4:2]= | 000 | 001 | 010 | 011 | 100 | 101 | 110 |
|---|---|---|---|---|---|---|---|
| op[6:5]=00 | Loads | F-ext | Fences | Arithm | AUIPC | RV64I | |
| op[6:5]=01 | Stores | F-ext | A-ext | Arithm | LUI | RV64I | |
| op[6:5]=10 | F-ext | F-ext | F-ext | F-ext | F-ext | RV128I | |
| op[6:5]=11 | Branches | JALR | JAL | System | RV128I |
Least significant byte of an instruction by class
| Byte | _3 | _7 | _B | _F |
|---|---|---|---|---|
| 0_/8_ | Loads | F-ext | Fences | |
| 1_/9_ | Arithm. (I) | AUIPC | RV64I | |
| 2_/A_ | Stores | F-ext | A-ext | |
| 3_/B_ | Arithm. (R) | LUI | RV64I | |
| 4_/C_ | F-ext | F-ext | F-ext | |
| 5_/D_ | F-ext | RV128I | ||
| 6_/E_ | Branches | JALR | JAL | |
| 7_/F_ | System | RV128I |