RISC-V basics

The basic sets and extensions

The basic instruction sets are:

• RV32I for 32-bit integers and addresses;
• RV64I for 64-bit integers and addresses;
• Some thought was given to RV128I as well.

A specific implementation MUST implement the basic set (allowing for software emulation of some instructions), and CAN implement standard and non-standard extensions.

Most common standard extensions:

• integer Multiplication
• integer Atomic operations
• single-precision (32bit) Floating-point operations
• Double-precision (64bit) floating-point operations
• Compressed instruction encoding

The General variant, RVnnG, is a shortcut for RVnnIMAFD

A popular compilation target is the GC combination:

$ rustup target list | grep riscv
riscv32i-unknown-none-elf
riscv32imac-unknown-none-elf
riscv32imc-unknown-none-elf
riscv64gc-unknown-linux-gnu
riscv64gc-unknown-none-elf 
riscv64imac-unknown-none-elf

Endianness

The base set memory system is assumed to be little-endian in respect to parcels.

16-bit parcels can be of any encoding, e.g.

    // Example: store x2 at x3 in native endianness
    sh   x2, 0(x3)    // store the low parcel of x2 at x3
    srli x2, x2, 16   // right-shift the integer by 16 bit
    sh   x2, 2(x3)    // store high parcel of x3

Exceptions, traps, interrupts

Exceptions are caused by not being to proceed with the normal execution of a thread. Trap is a synchronous transfer of control to a trap handler (usually executed in a more privileged environment).

Interrupts are caused by events external to the current thread of execution.